1. Field of the Invention
The present invention generally relates to the field of semiconductor integrated circuit (IC) packaging. In particular the present invention relates to an improved multi-chip ball grid array (BGA) package, which can be utilized with IC chips of identical or similar sizes, and a method of manufacturing the same.
2. Discussion of the Related Art
Semiconductors are materials that have characteristics of insulators and conductors. In today's technology, semiconductor materials have become extremely important as the basis for transistors, diodes, and other solid-state devices. Semiconductors are usually made from germanium or silicon, but selenium and copper oxide, as well as other materials are also used. When properly made, semiconductors will conduct electricity in one direction better than they will in the other direction.
Currently, emerging electronic product applications create a set of challenges for the IC packaging industry. Once the IC chips have been produced and encapsulated in semiconductor packages, they may be used in a wide variety of electronic appliances. The variety of the electronic devices which incorporate semiconductor packages has grown dramatically in recent years and includes cellular phones, portable computers, hand-held devices, and many others. Each of these devices typically includes a motherboard on which a number of semiconductor packages are secured to provide multiple electronic functions. As consumer demand increases, the size of these devices decreases and the cost is reduced. Therefore, it is increasingly desirable to reduce the profile of the integrated semiconductor packages so that the resultant electronic systems can be incorporated into more compact devices and products.
Recently, multi-chip packaging, which is a special field of IC packaging that relates to the assembly of multiple semiconductor chips within a single IC package entity, has become increasingly popular. This popularity is driven by an industry demand to package more functional silicon content into a smaller package at a lower cost Packaging two or more silicon chips within a single package reduces the related cost and also reduces the area required on the printed circuit boards, on which the IC package is mounted. In addition, multi chip packaging enables close proximity of chips resulting in shorter electronic signal paths between chips in the package. This reduces electronic signal travel time and improves overall speed and performance. Further, multi-chip packages save considerable mounting area, thus increasing valuable layout flexibility.
Multi-chip packages, in combination with BGA technology, are viewed as part of the solution for the widening gap between silicon I/O density and performance and the material capabilities of the package and board/substrate structure. Multi-chip packages can be viewed as standard single-chip packages modified to accommodate both multiple chips and passive components in order to provide the user with higher functionality integration. Typically, most multi-chip packages incorporate between two and six chips and are packaged in a conventional BGA.
The advantages of multi-chip packaging are numerous. For example, it allows for greater functionality in a time-to-market window that cannot be met through silicon integration. Effective use of multi-chip packages yields increased density and performance and reduced size and weight at the board or system level, while also reducing board area and routing complexity. Often, board layer reduction offsets the additional costs of using multi-chip packages. Additional benefits of multi chip packaging include design optimization through use of the most cost-effective silicon solutions and the ability to assemble packages utilizing different semiconductor technologies, die geometries, or types of chips in the same package.
This special field of IC packaging increases the value of high-speed designs, assembly processes and materials incorporated into a multi-chip package. Packaging chips together in this manner also facilitates the process of assembling stacked die or multi level, two-sided packages. The incorporation of different interconnection technologies, such as flip-chip or wire bond, into the multi-chip package is easily accommodated using this technology.
Typically, in multi-chip packaging, the component chips can be stacked vertically or can be arranged side by side within the package body. FIGS. 1A and 1B show examples of multi-chip packages utilizing stacked and side by side arrangements, respectively. Interconnections between chips and the external terminals of the package can be achieved through conventional wire bonding, as shown in FIGS. 1A and 1B, bumps in flip chip fashion, lead bonding, or through combinations of the above mentioned techniques. Chips stacked vertically require less package body area and therefore less space on the printed circuit board compared to those arranged side-by-side. Stacked chips therefore are generally the preferred method used in multi-chip packaging. However, there are several fundamental difficulties in chip stacking relating to stacking chips of similar sizes and to certain bond pad layout designs.
As shown in FIG. 1A, conventional chip-stacking technology comprises mounting a first IC chip 115A on a substrate 101 and then mounting a second chip 116A on top of the first chip 115A The first chip 115A is coupled to the substrate though a number of thin wires 121A linking bond pads (not shown) on the top surface of the first chip 115A to conductive material 103 on the top surface of the substrate 101. This method requires that a certain portion of the top surface of the first chip 115A, including bond pads, be free to connect to the thin wires 121A. Therefore, the second chip 116A must have a smaller footprint than the first chip 115A. If the second chip 116A were as large or larger than the first chip 115A, there would be no space on the top surface of the first chip 115A for the bond pads to be connected to the thin wires 121A.
As shown in FIG. 1B, multi-chip packaging utilizes chips arranged side by side within the package body. This packaging technology comprises mounting a first IC chip 115B on a substrate 101 and then mounting a second chip 116B beside the first chip 115A on the substrate 101. Both the first chip 115B and the second chip 116B are coupled to the substrate though a number of thin wires 121B linking bond pads (not shown) on the top surfaces of the first chip 115B and second chip 116B to conductive material 103 on the top surface of the substrate 101.
Thus, one current limitation of chip stacking technology is that chips of similar sizes with periphery bond pad layout designs, cannot be stacked directly on each other because the bonding pads of the bottom chip would be blocked by the upper chip.
For chips with non-periphery bond pad layout design, i.e. those with bond pads substantially centrally located on the surface of the chip, the probability that the bond pads of the bottom chip will be blocked is high even when smaller chips are stacked on top.
The present invention provides a feasible solution to these problems related to chip-stacking. The invention increases the functional capacity of semiconductor IC chips, while significantly reducing the need for package body area and printed circuit board space. The invention also enables an increase in yield.
Yield is the ratio of the useable components of an end package to those initially submitted for processing. Yield can be assessed at any input-output stage in processing, and must be carefully defined and understood. Often, the yield of a wafer is not very high. Therefore, it is important to determine which chips are defective and which chips are functional before the chips are packaged. Through a testing process, defective chips are discarded or repaired so that only functional chips are packaged in the final electronic devices.
It is increasingly important to know whether a chip is functional before it is packaged, because more and more chips are packed into individual multi-chip modules. Without testing, the compounded effect of the individual yields of multiple chips can result in very low yields for multi-chip modules. Therefore, there is a need for an improved method allowing for the testing of component chips before fill assembly.
The present invention also provides for facilitated product testing. It enables manufacturers to test the functional status of a chip prior to mounting it on a base substrate structure. This reduces the risk of combining a bad chip with a good one in multi-chip packaging (generally a non-reversible process) and thereby improves the final yield of the package.